The technical field of this invention is digital device functional blocks, used in microprocessors and more specifically used in digital signal processors.
The expanded direct memory access processor is the subject of U.S. patent application Ser. No. 09/713,609 filed contemporaneously with this application, entitled EXPANDED DIRECT MEMORY ACCESS PROCESSOR WITH HUB AND PORTS ARCHITECTURE. The expanded direct memory access processor provides a significant basic improvement in data transfer techniques in complex digital systems and allows, along with many other features, for uniform implementation of port interfaces at the periphery of such systems. The expanded direct memory access processor is an interconnection network which performs the task of communication throughout the processor system and its peripherals in a centralized function. Within the expanded direct memory access processor, a system comprised of a main hub and ports tied together by multiple pipelines is the medium for all data communications among processors and peripherals.
While the main hub controls the data transfers between the ports, processors or peripherals, the ports themselves control the actual device access. There are two types of ports, internal and external. Internal-ports connect to the local memory elements of processors located on the same chip as the expanded direct memory access processor. These internal ports communicate to the processor and/or on-chip memory. External ports connect to all the remaining peripherals through the external ports interface.
The external ports interface preferably used in a digital signal processor employing an expanded direct memory access processor is partitioned into two sections. These are the hub interface unit and the application unit. The interface between the hub interface unit and the application unit is the subject of this invention.
This invention relates to the operations and interconnections which are required for communication between the hub interface unit (HIU) and the application unit (AU) of the external ports of an expanded direct memory access processor. The hub interface unit handles this task, performing data buffering and frequency synchronization. This provides for the creation of very simple external peripherals, which do not require extensive buffers and buffer management. This also provides for these external peripherals to run at their own natural frequency, without need for their own synchronization to the internal interface.
The hub interface unit performs this synchronization by using the core clock frequency for the majority of its logic. The application unit clock frequency is used for the remaining application unit interface logic. The application unit performs all the peripheral access commands requested by the expanded direct memory access processor on behalf of the processors. The application unit receives commands from the hub interface unit and performs the required data read/write to the peripheral. This may require physically passing requests through I/O pins to an external device. The application unit may run at a single frequency since the hub interface unit handles synchronizing the commands and data to the expanded direct memory access processor frequency. Because the hub interface unit provides buffering, the application unit need not contain large buffers. This allows the application unit to simply retrieve requested data and deliver it to the hub interface unit immediately.
One aspect of this invention is the interface between the hub interface unit and application unit. The application units are designed to provide configurable peripherals to be connected to the expanded direct memory access processor without alteration to the extended direct memory access processor design. Any hub interface unit and any application unit communicate with each other in the same manner with the same interface of hardware and signal connections. In addition, configuration signals are passed from the application unit to the expanded direct memory access processor to define the configuration to which the expanded direct memory access processor must conform. This allows a single expanded direct memory access processor design to be re-used in a multitude of products which have separate and different peripheral sets.